Function core::arch::mips::__msa_fsaf_d
source · pub unsafe fn __msa_fsaf_d(a: v2f64, b: v2f64) -> v2i64
🔬This is a nightly-only experimental API. (
stdarch_mips
#111198)Available on (MIPS or MIPS-64) and target feature
msa
and MIPS only.Expand description
Vector Floating-Point Signaling Compare Always False
Set all bits to 0 in vector (two signed 64-bit integer numbers) elements.
Signaling and quiet NaN elements in vector a
(two 64-bit floating point numbers)
or b
(two 64-bit floating point numbers) signal Invalid Operation exception.
In case of a floating-point exception, the default result has all bits set to 0.